1. Field of the Invention
This invention relates to semiconductor structures and more particularly to an integrated semiconductor transistor structure having an annular collector/subcollector region.
2. Description of the Prior Art
Integrated semiconductor transistor structures are well known in the art. Traditionally, a highly doped n+ subcollector region is diffused into a major surface of semiconductor substrate. An epitaxial layer is then deposited over the substrate and the subcollector partially out-diffuses into the epitaxial layer. A base region is then diffused into the epitaxial region with a p type impurity. An n type impurity such as arsenic or phosphorous, for example, is then diffused into the base region forming the emitter region of the transistor.
With the foregoing structure, it is known that transistor action takes places primarily in the area under the emitter region. Thus, a large area between the base and collector/subcollector region as well as between the collector/subcollector region and the substrate do not contribute to the transistor action while adding capacitance, which is undesirable.
It is also known that the size of the emitter diffusion effects the threshold base to emitter voltage (V.sub.be) of a transistor. A transistor with a smaller emitter can switch from conduction to nonconduction and vice versa faster but has the disadvantage of reduced noise tolerance. In the formation of transistor structures as presently known, the space required by a transistor is changed in order to obtain different V.sub.be characteristics.